Technical Field
The present disclosure relates to an image processor.
Related Art
An encoder according to one technique of H.264 includes a DRAM as image storage for storing a local decoded image, an SRAM that holds a reference image read from the DRAM, and a motion search unit that performs motion search on the basis of a reference image to generate a prediction block. Then the encoder performs DCT transformation, quantization, and entropy coding on a prediction error, which is a difference between a target macroblock and a prediction block, so as to realize highly efficient data compression. The SRAM stores an image in a predetermined search range, which is slightly broader than a macroblock, of a local decoded image of one frame stored in the DRAM, as a reference image.
A decoder according to one technique of H.264 includes a DRAM as image storage for storing a decoded image, an SRAM that holds a reference image read from the DRAM, and a motion search unit that performs motion search on the basis a reference image to generate a prediction block. Then the decoder performs entropy decoding, dequantization, and inverse DCT transformation on the input coded data to generate a prediction error, and reconstitutes the input image on the basis of the prediction block and the prediction error to generate a decoded block. According to H.264, decoding is performed in a unit of a rectangular macroblock, and thus in writing a decoded block to a DRAM, a write access to the DRAM is performed with an address format in which addresses are successive between each row in a rectangular region (hereinafter, “codec format”).
JP5,147,102B describes a method for accessing a memory suitable for a write access in a unit of a macroblock, by performing burst transfer while switching banks of the memory in writing a decoded image to the memory.
The encoder according to the above-described technique requires, if no highly correlative block of a target macroblock is found in a reference image (that is, a cache mishit), reading a reference image in another region from the DRAM and storing in the SRAM again. Thus read access to the DRAM occurs, causing prolonged processing time. Moreover, recent enhanced resolution of cameras and televisions increases access to data in the DRAM, while band of a bus in DRAM is becoming severe, which requires avoiding an access to the DRAM as much as possible to reduce band of a bus.
Furthermore, the decoder according to the above-described technique writes a decoded block to the DRAM in the codec format. Displaying the decoded image on a display device, however, requires image data in an address format in which addresses are successive horizontally in an image (raster format), and thus a decoded image in the codec format cannot be used without change. Thus a format conversion circuit needs to be implemented for conversion from the codec format into the raster format. The format conversion circuit converts the decoded image in the codec format read from the DRAM into the raster format and writes the converted decoded image to the DRAM. Thus read access from and write access to the DRAM occur due to format conversion, causing prolonged delay time for display and increase in power consumption by the DRAM. Moreover, as described above, reduction in band of a bus by avoiding an access to the DRAM as much as possible is required.